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INTEGRATED CIRCUITS
80C32/87C52 CMOS single-chip 8-bit microcontrollers
Product specification IC20 Data Handbook 1996 Aug 16
Philips Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DESCRIPTION
The Philips 80C32/87C52 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. The 87C52 contains an 8k x 8 EPROM and the 80C32 is ROMless. Both contain a 256 x 8 RAM, 32 I/O lines, three 16-bit counter/timers, a six-source, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the 80C32/87C52 has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. See 80C52/80C54/80C58 datasheet for ROM device specifications.
PIN CONFIGURATIONS
P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CERAMIC AND PLASTIC DUAL IN-LINE PACKAGE 40 VDD 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/V PP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
FEATURES
* 80C51 based architecture * 8032 compatible
- 8k x 8 EPROM (87C52) - ROMless (80C32) - 256 x 8 RAM - Three 16-bit counter/timers - Full duplex serial channel - Boolean processor
WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS
SU00060
* Memory addressing capability
- 64k ROM and 64k RAM
* Power control modes:
- Idle mode - Power-down mode
* CMOS and TTL compatible * Three speed ranges:
- 3.5 to 16MHz - 3.5 to 24MHz - 3.5 to 33MHz
* Five package styles * Extended temperature ranges * OTP package available
1996 Aug 16
2
853-1562 17195
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ORDERING INFORMATION
ROMless P80C32EBP N P80C32EBA A EPROM1 P87C52EBP N P87C52EBA A P87C52EBF FA P87C52EBL KA P80C32EBB B P80C32EFP N P80C32EFA A P87C52EBB B P87C52EFP N P87C52EFA A P87C52EFF FA P80C32EFB B P80C32IBP N P80C32IBA A P80C32IBB B P87C52IBF FA P87C52IBL KA P80C32IFP N P80C32IFA A P80C32IFB B P87C52IFF FA P80C32NBA A P80C32NBP N P80C32NBB B P80C32NFA A P80C32NFP N P80C32NFB B UV P87C52IFP N P87C52IFA A UV UV OTP OTP P87C52EFB B P87C52IBP N P87C52IBA A OTP OTP UV UV OTP OTP OTP UV OTP OTP OTP TEMPERATURE RANGE C AND PACKAGE 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Ceramic Dual In-line Package 0 to +70, Ceramic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Ceramic Dual In-line Package -40 to +85, Plastic Quad Flat Pack 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack 0 to +70, Ceramic Dual In-line Package 0 to +70, Ceramic Leaded Chip Carrier -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Quad Flat Pack -40 to +85, Ceramic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Quad Flat Pack FREQ MHz 16 16 16 16 16 16 16 16 16 24 24 24 24 24 24 24 24 24 33 33 33 33 33 33 DRAWING NUMBER SOT129-1 SOT187-2 0590B 1472A SOT307-2 SOT129-1 SOT187-2 0590B SOT307-2 SOT129-1 SOT187-2 SOT307-2 0590B 1472A SOT129-1 SOT187-2 SOT307-2 0590B SOT187-2 SOT129-1 SOT307-2 SOT187-2 SOT129-1 SOT307-2
NOTE: 1. OTP = One Time Programmable EPROM. UV = UV erasable EPROM 2. For 33MHz ROM 80C52 operation, see 80C52/80C54/80C58 data sheet.
1996 Aug 16
3
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39
1
33
LCC 11 17 29
PQFP
23
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC* T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2 INT1/P3.3 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6 P1.7 RST RxD/P3.0 NC* TxD/P3.1 INT0/P3.2 INT1/P3.3 T0/P3.4 T1/P3.5 WR/P3.6 RD/P3.7 XTAL2 XTAL1
12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7
22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* T2/P1.0 T2EX/P1.1 P1.2 P1.3 P1.4
* DO NOT CONNECT
SU00061
* DO NOT CONNECT
SU00062
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2 T2 T2EX RST EA/VPP PSEN SECONDARY FUNCTIONS ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 PORT 2
PORT 3
ADDRESS BUS
SU00063
1996 Aug 16
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
ROM/ EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU
PCON T2CON TL1
SCON TH0 TH2
TMOD TL0 TL2 IE
TCON TH1 RCAP2H IP
BUFFER
PSW
RCAP2L SBUF
INTERRUPT, SERIAL PORT AND TIMER BLOCKS
PC INCREMENTER
PROGRAM COUNTER PSEN ALE EA RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00064
1996 Aug 16
5
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Table 1.
SYMBOL ACC* B* DPTR: DPH DPL
8XC52 Special Function Registers
DESCRIPTION Accumulator B register Data pointer (2 bytes) Data pointer high Data pointer low DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION ADDRESS MSB LSB E0H F0H 83H 82H AF AE - BE - AD ET2 BD PT2 AC ES BC PS AB ET1 BB PT1 AA EX1 BA PX1 A9 ET0 B9 PT0 A8 EX0 B8 PX0 xx000000B 0x000000B E7 F7 E6 F6 E5 F5 E4 F4 E3 F3 E2 F2 E1 F1 E0 F0 RESET VALUE 00H 00H 00H 00H
IE*
Interrupt enable
A8H
EA BF
IP*
Interrupt priority
B8H
-
87 P0* Port 0 80H AD7
86 AD6
85 AD5
84 AD4
83 AD3
82 AD2
81 AD1
80 AD0 FFH
97 P1* Port 1 90H -
96 -
95 -
94 -
93 -
92 -
91 T2EX
90 T2 FFH
A7 P2* Port 2 A0H A15
A6 A14
A5 A13
A4 A12
A3 A11
A2 A10
A1 A9
A0 A8 FFH
B7 P3* PCON1 Port 3 Power control B0H 87H RD SMOD
B6 WR -
B5 T1 -
B4 T0 -
B3 INT1 GF1
B2 INT0 GF0
B1 TxD PD
B0 RxD IDL FFH 0xxxxxxxB
D7 PSW* RCAP2H# RCAPL# SBUF Program status word Capture high Capture low Serial data buffer D0H CBH CAH 99H 9F SCON* SP Serial controller Stack pointer 98H 81H 8F TCON* Timer control 88H TF1 SM0 CY
D6 AC
D5 F0
D4 RS1
D3 RS0
D2 OV
D1 -
D0 P 00H 00H 00H xxxxxxxxB
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 07H
8E TR1
8D TF0
8C TR0
8B IE1
8A IT1
89 IE0
88 IT0 00H
CF T2CON*# TH0 TH1 TH2# TL0 TL1 TL2# Timer 2 control Timer high 0 Timer high 1 Timer high 2 Timer low 0 Timer low 1 Timer low 2 C8H 8CH 8DH CDH 8AH 8BH CCH TF2
CE EXF2
CD RCLK
CC TCLK
CB EXEN2
CA TR2
C9 C/T2
C8 CP/RL2 00H 00H 00H 00H 00H 00H 00H
TMOD Timer mode 89H GATE C/T M1 M0 GATE * Bit addressable # SFRs are modified from or added to the 80C51 SFRs. 1. Bits GF1, GF0, PD, and IDL of the PCON register are not implemented in the NMOS 8XC52.
C/T
M1
M0
00H
1996 Aug 16
6
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
PIN DESCRIPTION
PIN NO. MNEMONIC VSS VCC P0.0-0.7 DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C52. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Pins P1.0 and P1.1 also. Port 1 also receives the low-order address byte during program memory verification. Port 1 also serves alternate functions for timer 2: T2 (P1.0): Timer/counter 2 external count input. T2EX (P1.1): Timer/counter 2 trigger input. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 1FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
P1.0-P1.7
1-8
2-9
40-44 1-3
I/O
1 2 P2.0-P2.7 21-28
2 3 24-31
40 41 18-25
I I I/O
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE/PROG
30
33
27
I/O
PSEN
29
32
26
O
EA/VPP
31
35
29
I
XTAL1 XTAL2
19 18
21 20
15 14
I O
1996 Aug 16
7
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DIFFERENCES FROM THE 80C51 Special Function Registers
The special function register space is the same as the 80C51 except that the 80C32/87C52 contains the additional special function registers T2CON, RCAP2L, RCAP2H, TL2, and TH2. Since the standard 80C51 on-chip functions are identical in the 8XC52, the SFR locations, bit locations, and operation are likewise identical. The only exceptions are in the interrupt mode and interrupt priority SFRs (see Table 1).
transition at external input T2EX will also trigger the 16-bit reload and set EXF2. The auto-reload mode is illustrated in Figure 3. The baud rate generation mode is selected by RCLK = 1 and/or TCLK = 1. It will be described in conjunction with the serial port.
Serial Port
The serial port of the 8XC52 is identical to that of the 80C51 except that counter/timer 2 can be used to generate baud rates. In the 8XC52, Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (see Figure 1). Note that the baud rate for transmit and receive can be simultaneously different. Setting RCLK and/or TCLK puts Timer into its baud rate generator mode, as shown in Figure 4. The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software. Now, the baud rates in Modes 1 and 3 are determined by Timer 2's overflow rate as follows: Modes 1, 3 Baud Rate + Timer 2 Overflow Rate 16 The timer can be configured for either "timer" or "counter" operation. In the most typical applications, it is configured for "timer" operation (C/T2 = 0). "Timer" operation is a little different for Timer 2 when it's being used as a baud rate generator. Normally, as a timer it would increment every machine cycle (thus at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (thus at 1/2 the oscillator frequency). In that case the baud rate is given by the formula: Modes 1, 3 Baud Rate + 32 Oscillator Frequency [65536 * (RCAP2H, RCAP2L)]
Timer/Counters
In addition to timer/counters 0 and 1 of the 80C51, the 80C32/87C52 contains timer/counter 2. Like timers 0 and 1, timer 2 can operate as either an event timer or as an event counter. This is selected by bit C/T2 in the special function register T2CON (see Figure 1). It has three operating modes: capture, auto-load, and baud rate generator, which are selected by bits in the T2CON as shown in Table 2. In the Capture Mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter which upon overflowing sets bit TF2, the Timer 2 overflow bit, which can be used to generate an interrupt. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. (RCAP2L and RCAP2H are new special function registers in the 80C52.) In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt. The Capture Mode is illustrated in Figure 2. In the auto-reload mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 rolls over it not only sets TF2 but also causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2L and RCAP2H, which are preset by software. If EXEN2 = 1, then Timer 2 still does the above, but with the added feature that a 1-to-0
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
(MSB) TF2 Symbol TF2 EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 TR2 C/T2
(LSB) CP/RL2
Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
TR2 C/T2
T2CON.2 T2CON.1
CP/RL2
T2CON.0
SU00065
Figure 1. Timer/Counter 2 (T2CON) Control Register
1996 Aug 16
8
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
OSC
/ 12 C/T2 = 0 TL2 (8-bits) C/T2 = 1 TH2 (8-bits) TF2
T2 Pin
Control
TR2 Transition Detector
Capture Timer 2 Interrupt RCAP2L RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
OSC
/ 12 C/T2 = 0 TL2 (8-BITS) C/T2 = 1 TH2 (8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TF2 TIMER 2 INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 3. Timer 2 in Auto-Reload Mode
1996 Aug 16
9
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Timer 1 Overflow
NOTE: OSC. Freq. is divided by 2, not 12. /2 C/T2 = 0 TL2 (8-bits) C/T2 = 1 T2 Pin Control TH2 (8-bits) "1"
/2 "0" "1" SMOD "0" RCLK
OSC
/ 16 TR2 "1" Reload "0"
RX Clock
TCLK
Transition Detector
RCAP2L
RCAP2H
/ 16
TX Clock
T2EX Pin
EXF2
Timer 2 Interrupt
Control EXEN2 Note availability of additional external interrupt.
SU00068
Figure 4. Timer 2 in Baud Rate Generator Mode
Table 2.
0 0 1 X
Timer 2 Operating Modes
CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
RCLK + TCLK
Timer 2 as a baud rate generator is shown in Figure 4. This figure is valid only if RCLK + TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Therefore, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate generator, T2EX can be used as an extra external interrupt, if desired. It should be noted that when Timer 2 is running (TR2 = 1) in "timer" function in the baud rate generator mode, one should not try to read or write TH2 or TL2. Under these conditions the timer is being incremented every state time, and the results of a read or write may not be accurate. The RCAP registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. Turn the timer off (clear TR2) before accessing the Timer 2 or RCAP registers, in this case.
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. See Table 3 for set-up of timer 2 as a timer. See Table 4 for set-up of timer 2 as a counter.
Using Timer/Counter 2 to Generate Baud Rates
For this purpose, Timer 2 must be used in the baud rate generating mode. If Timer 2 is being clocked through pin T2 (P1.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16 And if it is being clocked internally, the baud rate is: Baud Rate + 32 Oscillator Frequency [65536 * (RCAP2H, RCAP2L)]
To obtain the reload value for RCAP2H and RCA02L, the above equation can be rewritten as: RCAP2H, RCAP2L + 65536 * Oscillator Frequency 32 Baud Rate
1996 Aug 16
10
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Interrupts
The 80C32/87C52 has 6 interrupt sources. All except TF2 and EXF2 are identical sources to those in the 80C51. The Interrupt Enable Register and the Interrupt Priority Register are modified to include the additional 80C32/87C52 interrupt sources. The operation of these registers is identical to the 80C51. In the 80C32/87C52, the Timer 2 Interrupt is generated by the logical OR of TF2 and EXF2. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and the bit will have to be cleared in software. All of the bits that generate interrupts can be set or cleared by software, with the same result as though it has been set or cleared
by hardware. That is, interrupts can be generated or pending interrupts can be canceled in software. The interrupt vector addresses and the interrupt priority for requests in the same priority level are given in the following: Vector Priority Within Address Level IE0 0003H (highest) TF0 000BH IE1 0013H TF1 001BH RI + TI 0023H TF2 + EXF2 002BH (lowest) Source
1. 2. 3. 4. 5. 6.
Note that they are identical to those in the 80C51 except for the addition of the Timer 2 (TF1 and EXF2) interrupt at 002BH and at the lowest priority within a level.
Table 3.
Timer 2 as a Timer
MODE INTERNAL CONTROL (Note 1) T2CON EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H
16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only
00H 01H 34H 24H 14H
Table 4.
Timer 2 as a Counter
MODE INTERNAL CONTROL (Note 1) 16-bit 02H TMOD EXTERNAL CONTROL (Note 2) 0AH
Auto-Reload 03H 0BH NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when timer 2 is used in the baud rate generator mode.
1996 Aug 16
11
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol, page 4. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register PCON.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles.
DESIGN CONSIDERATIONS
At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Table 5 shows the state of I/O ports during low current operating modes. As a precaution to coming out of an unexpected power down, INT0 and INT1 should be disabled prior to enterring power down.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all
Table 5. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
1996 Aug 16
12
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C52) DC and AC parameters not included here are the same as in the commercial temperature range table.
DC ELECTRICAL CHARACTERISTICS
Tamb = -40C to +85C, VCC = 5V 10%, VSS = 0V TEST SYMBOL VIL VIL1 VIH VIH1 IIL ITL ICC PARAMETER Input low voltage, except EA Input low voltage to EA Input high voltage, except XTAL1, RST Input high voltage to XTAL1, RST Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 3 Power supply current: Active mode Idle mode Power-down mode VIN = 0.45V VIN = 2.0V VCC = 4.5-5.5V, Frequency range = 3.5 to 16MHz CONDITIONS MIN -0.5 0 0.2VCC+1 0.7VCC+0.1 LIMITS MAX 0.2VCC-0.15 0.2VCC-0.35 VCC+0.5 VCC+0.5 -75 -750 32 5 50 UNIT V V V V A A mA mA A
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.5 15 1.5 UNIT C C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1996 Aug 16
13
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V (87C52) Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V (80C32) TEST SYMBOL VIL VIL1 VIH VIH1 VOL VOL1 VOH PARAMETER Input low voltage, except Input low voltage to EA7 RST7 EA7 CONDITIONS MIN -0.5 0 0.2VCC+0.9 0.7VCC IOL = 1.6mA2 IOL = 3.2mA2 IOH = -60A, IOH = -25A IOH = -10A IOH = -800A, IOH = -300A IOH = -80A VIN = 0.45V 37 See note 4 VIN = VIL or VIH See note 6 Tamb = 0 to 70C Tamb = -40 to +85C 50 11.5 1.3 3 32 5 50 75 300 15 mA mA A A k pF 2.4 0.75VCC 0.9VCC 2.4 0.75VCC 0.9VCC -50 -650 10 LIMITS TYP1 MAX 0.2VCC-0.1 0.2VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45 UNIT V V V V V V V V V V V V A A A
Input high voltage, except XTAL1, Input high voltage, XTAL1, RST7
Output low voltage, ports 1, 2, 39 Output low voltage, port 0, ALE, PSEN9 Output high voltage, ports 1, 2, 3, ALE, PSEN3
VOH1
Output high voltage (port 0 in external bus mode)
IIL ITL ILI ICC
Logical 0 input current, ports 1, 2, 37 Logical 1-to-0 transition current, ports 1, 2, Input leakage current, port 0 Power supply current:7 Active mode @ 16MHz5 Idle mode @ 16MHz Power-down mode
RRST CIO
Internal reset pull-down resistor Pin capacitance10
NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies is given by: Active mode: ICCMAX = 1.5 x FREQ + 8.0: Idle mode: ICCMAX = 0.14 x FREQ +2.31, where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 12. 6. See Figures 13 through 16 for ICC test conditions. 7. These values apply only to Tamb = 0C to +70C. For Tamb = -40C to +85C, see table on previous page. 8. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 9. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA (*NOTE: This is 85C specification.) Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 67mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. This limit is for plastic packages. For ceramic packages, the maximum limit is 20pF.
1996 Aug 16
14
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V (87C52)1, 2, 3 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 8 8 8 8 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 750 492 8 0 12tCLCL 10tCLCL-133 2tCLCL-117 0 ns ns ns ns 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 7 6, 7 6, 7 9 9 9 9 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time 23 20 20 20 20 137 122 13 13 287 0 103 tCLCL-40 20 20 0 65 350 397 239 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 0 tCLCL+40 tCLCL-tCLCX tCLCL-tCHCX 20 20 275 275 147 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 5 5 5 5 5 5 5 5 5 5 5 5 PARAMETER Oscillator frequency Speed versions ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 37 207 10 32 142 82 0 tCLCL-25 5tCLCL-105 10 :E 85 22 32 150 tCLCL-30 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
External Clock
tXHDV 8 Clock rising edge to input data valid 492 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C32/52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interface.
1996 Aug 16
15
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 24MHz CLOCK SYMBOL 1/tCLCL FIGURE 5 PARAMETER Oscillator frequency Speed versions : I :N ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 505 283 3 0 17 17 17 5 5 12tCLCL 10tCLCL-133 2tCLCL-80 0 75 92 12 17 162 0 67 tCLCL-25 17 17 0 55 183 210 175 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 0 tCLCL+25 tCLCL-tCLCX tCLCL-tCHCX 5 5 363 170 19 0 5 150 150 118 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 41 46 0.3 5 82 0 5 0 17 128 10 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 33 92 108 141 17 80 65 0 tCLCL-25 5tCLCL-80 10 82 82 62 43 17 17 102 tCLCL-25 3tCLCL-45 3tCLCL-60 0 5 72 10 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 5 46 31 MAX 24 3.5 21 5 5 56 33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 33MHz CLOCK MIN MAX UNIT MHz
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
5 5 5 5 5 5 5 5 5 5 5 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 6, 7 7 6, 7 6, 7 9 9 9 9 8 8 8 8
External Clock
tXHDV 8 Clock rising edge to input data valid 283 10tCLCL-133 170 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 8XC52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz "AC Electrial Characteristics", page 15. 1996 Aug 16 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL= Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 5. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 6. External Data Memory Read Cycle
1996 Aug 16
17
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00069
Figure 7. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 8. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 9. External Clock Drive
1996 Aug 16
18
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
VCC-0.5
0.2VCC+0.9 0.2VCC-0.1
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
SU00010
Figure 10. AC Testing Input/Output
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00011
Figure 11. Float Waveform
65
60 MAX ACTIVE MODE ICCMAX = 1.5 X FREQ. + 8.0
55
50
45
40
35 ICC mA 30 TYP ACTIVE MODE 25
20
15
10 MAX IDLE MODE 5 TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz FREQ AT XTAL1
SU00070B
Figure 12. ICC vs. FREQ Valid only within frequency specifications of the device under test
1996 Aug 16
19
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 13. ICC Test Condition, Active Mode All other pins are disconnected
Figure 14. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 15. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 16. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
1996 Aug 16
20
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EPROM CHARACTERISTICS
The 87C52 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C52 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C52 manufactured by Philips. Table 6 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 17 and 18. Figure 19 shows the circuit configuration for normal program memory verification.
Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 19. The other pins are held at the `Verify Code Data' levels indicated in Table 6. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 97H indicates 87C52
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 17. Note that the 87C52 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 17. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 6 are held at the `Program Code Data' levels indicated in Table 6. The ALE/PROG is pulsed low 25 times as shown in Figure 18. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 6, and which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-s/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000W/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state.
Table 6. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 Pgm security bit 2 RST 1 1 1 1 1 1 PSEN 0 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* 0* EA/VPP 1 VPP 1 VPP VPP VPP P2.7 0 1 0 1 1 1 P2.6 0 0 0 0 1 1 P3.7 0 1 1 1 1 0 P3.6 0 1 1 0 1 0
NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V 0.25V. 3. VCC = 5V10% during programming and verification. 4. *ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s. TMTrademark phrase of Intel Corporation. 1996 Aug 16 21
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C52 P0 PGM DATA +12.75V 25 100s PULSES TO GROUND 0 1 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00071
Figure 17. Programming Configuration
1 ALE/PROG: 0
25 PULSES
1 ALE/PROG: 0
10s MIN
100s+10
SU00018
Figure 18. PROG Waveform
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C52 P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A12
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.4
SU00072
Figure 19. Program Verification
1996 Aug 16
22
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 20) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s PARAMETER MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
NOTE: * FOR PROGRAMMING VERIFICATION SEE FIGURE 17.
FOR VERIFICATION CONDITIONS SEE FIGURE 19.
Figure 20. EPROM Programming and Verification
1996 Aug 16
23
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1996 Aug 16
24
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1996 Aug 16
25
0590B
1996 Aug 16
SEE NOTE 6 0.098 (2.49) 0.040 (1.02)
Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
853-0590B 06688
0.098 (2.49) 0.040 (1.02)
NOTES: 1. Controlling dimension: Inches. Millimeters are shown in parentheses. 2. Dimension and tolerancing per ANSI Y14. 5M-1982. 3. "T", "D", and "E" are reference datums on the body and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. 4. These dimensions measured with the leads constrained to be perpendicular to plane T. 5. Pin numbers start with Pin #1 and continue counterclockwise to Pin #40 when viewed from the top. 6. Denotes window location for EPROM products.
-E-
0.598 (15.19) 0.571 (14.50)
PIN # 1 2.087 (53.01) 2.038 (51.77)
0.100 (2.54) BSC
-D-
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
26
0.225 (5.72) MAX. 0.175 (4.45) 0.145 (3.68) 0.165 (4.19) 0.125 (3.18) 0.055 (1.40) 0.020 (0.51) ED 0.010 (0.254) 0.015 (0.38) 0.010 (0.25)
0.070 (1.78) 0.050 (1.27)
0.620 (15.75) 0.590 (14.99) (NOTE 4)
-T-
SEATING PLANE
BSC 0.600 (15.24) (NOTE 4) 0.695 (17.65) 0.600 (15.24)
0.023 (0.58) 0.015 (0.38)
T
80C32/87C52
Product specification
1472A
1996 Aug 16
3.05 (0.120) 2.29 (0.090) 0.38 (0.015) 6
Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
853-1472A 05854
1.02 (0.040) X 45 CHAMFER 45
17.65 (0.695) 17.40 (0.685) 16.89 (0.665) 16.00 (0.630) 3
NOTES: 1. All dimensions and tolerances to conform to ANSI Y14.5-1982. 2. UV window is optional. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum on each side. 4. Controlling dimension millimeters. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 6. Backside solder relief is optional and dimensions are for reference only.
0.51 (0.02) X 45 17.65 (0.695) 17.40 (0.685) 16.89 (0.665) 16.00 (0.630) 3 6
2
44-PIN CERQUAD J-BEND (K) PACKAGE
3 X 0.63 (0.025) R MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
0.73 + 0.08 (0.029 + 0.003) 1.27 (0.050) TYP. 0.25 (0.010) R MIN. 1.52 (0.060) REF. 45 TYP. 4 PLACES 0.15 (0.006) MIN.
90
27
1.02 + 0.25 (0.040 + 0.010) SEE DETAIL A 0.482 (0.019 + 0.002) SEATING PLANE BASE PLANE
+ 5 -10
17.65 (0.656) 17.40 (0.685)
1.27 (0.050)
40X
0.076 (0.003) MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
SEE DETAIL B
12.7 (0.500) NOMINAL
0.25 (0.010) 0.15 (0.006)
0.508 (0.020) R MIN.
8.13 (0.320) 7.37 (0.290)
8.13 (0.320) 7.37 (0.290)
DETAIL A TYP. ALL SIDES mm/(inch)
DETAIL B mm/(inch)
80C32/87C52
Product specification
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
1996 Aug 16
28
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
NOTES
1996 Aug 16
29
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C32/87C52
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.
INTEGRATED CIRCUITS
80C52/80C54/80C58 CMOS single-chip 8-bit microcontrollers
Product specification IC20 Data Handbook 1996 Aug 16
Philips Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DESCRIPTION
The 80C52/80C54/80C58 Single-Chip 8-Bit Microcontroller is manufactured in an advanced CMOS process and is a derivative of the 80C51 microcontroller family. The 80C52/80C54/80C58 has the same instruction set as the 80C51. This device provides architectural enhancements that make it applicable in a variety of applications for general control systems. The 80C52 contains 8k x 8 ROM memory, the 80C54 contains 16k x 8 ROM memory, and 80C58 contains 32k x 8 ROM memory, a volatile 256 x 8 read/write data memory, four 8-bit I/O ports, three 16-bit timer/event counters, a multi-source, four-priority-level, nested interrupt structure, an enhanced UART and on-chip oscillator and timing circuits. For systems that require extra capability, the 80C52/54/58 can be expanded using standard TTL compatible memories and logic. Its added features make it an even more powerful microcontroller for applications that require pulse width modulation, high-speed I/O and up/down counting capabilities such as motor control. It also has a more versatile serial channel that facilitates multiprocessor communications. See 87C52/80C32 and 87C54/87C58 data sheets for EPROM and ROMless devices.
PIN CONFIGURATIONS
T2/P1.0 1 T2EX/P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20 DUAL IN-LINE PACKAGE 40 VCC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA 30 ALE 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
FEATURES
* 80C51 central processing unit * Full static operation * 8k x 8 ROM: 80C52;
16k x 8 ROM: 80C54; 32k x 8 ROM: 80C58; all capable of addressing external memory to 64k bytes - Two level program security system - 64 byte encryption array
SU00740
* 256 x 8 RAM, expandable externally to 64k bytes * Speed range up to 33MHz * Operating voltage 5V 10% * Three 16-bit timer/counters
- T2 is an up/down counter
* 6 interrupt sources * 4 level priority * Four 8-bit I/O ports * Full-duplex enhanced UART
- Framing error detection - Automatic address recognition
* Power control modes
- Idle mode - Power-down mode
* Once (On Circuit Emulation) Mode * Five package styles * Programmable clock out * Low EMI (Inhibit ALE) * Second DPTR register * Asynchronous port reset
1996 Aug 16 2 853-1470 17196
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ORDERING INFORMATION
ROM 8k x 8 P80C52EBPN P80C52EBAA P80C52EBBB P80C52EFP N P80C52EFA A P80C52EFB B P80C52IBP N P80C52IBA A P80C52IBB B P80C52IFP N P80C52IFA A P80C52IFB B P80C52NBAA P80C52NBPN P80C52NBBB P80C52NFA A P80C52NFPN P80C52NFBB ROM 16k x 8 P80C54EBPN P80C54EBAA P80C54EBBB P80C54EFP N P80C54EFA A P80C54EFB B P80C54IBP N P80C54IBA A P80C54IBB B P80C54IFP N P80C54IFA A P80C54IFB B P80C54NBAA P80C54NBPN P80C54NBBB P80C54NFA A P80C54NFPN P80C54NFBB ROM 32k x 8 P80C58EBPN P80C58EBAA P80C58EBBB P80C58EFP N P80C58EFA A P80C58EFB B P80C58IBP N P80C58IBA A P80C58IBB B P80C58IFP N P80C58IFA A P80C58IFB B P80C58NBAA P80C58NBPN P80C58NBBB P80C58NFA A P80C58NFPN P80C58NFBB TEMPERATURE RANGE C AND PACKAGE 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Quad Flat Pack 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Quad Flat Pack 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Quad Flat Pack -40 to +85, Plastic Leaded Chip Carrier -40 to +85, Plastic Dual In-line Package -40 to +85, Plastic Quad Flat Pack FREQ MHz 16 16 16 16 16 16 24 24 24 24 24 24 33 33 33 33 33 33 DRAWING NUMBER SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT129-1 SOT187-2 SOT307-2 SOT187-2 SOT129-1 SOT307-2 SOT187-2 SOT129-1 SOT307-2
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2 T2 T2EX RST EA PSEN SECONDARY FUNCTIONS ALE RxD TxD INT0 INT1 T0 T1 WR RD PORT 1 PORT 2
PORT 3
ADDRESS BUS
SU00732
1996 Aug 16
3
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH 8
PORT 2 DRIVERS 8
PORT 2 LATCH
ROM
16 B REGISTER STACK POINTER
ACC
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU SFRs PSW TIMERS
BUFFER
PC INCREMENTER 8 PROGRAM COUNTER 16
PSEN ALE EA RST PD TIMING AND CONTROL
INSTRUCTION REGISTER
MULTIPLE DPTRs
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00733B
1996 Aug 16
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Table 1.
SYMBOL ACC* AUXR# AUXR1# B* DPTR: DPH DPL IE* IP* IPH# P0* P1* P2* P3* PCON#1 PSW* RACAP2H# RACAP2L# SADDR# SADEN# SBUF SCON* SP TCON* T2CON* T2MOD# TH0 TH1 TH2# TL0 TL1 TL2#
80C52/80C54/80C58 Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary 1 B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Timer 2 Capture High Timer 2 Capture Low Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer High 2 Timer Low 0 Timer Low 1 Timer Low 2 DIRECT ADDRESS E0H 8EH A2H F0H 83H 82H AF A8H B8H B7H 80H 90H A0H B0H 87H D0H CBH CAH A9H B9H 99H 9F 98H 81H 8F 88H C8H C9H 8CH 8DH CDH 8AH 8BH CCH TF1 CF TF2 - 8E TR1 CE EXF2 - 8D TF0 CD RCLK - 8C TR0 CC TCLK - 8B IE1 CB EXEN2 - 8A IT1 CA TR2 - 89 IE0 C9 C/T2 T2OE 88 IT0 C8 CP/RL2 DCEN 00H xxxxxx00B 00H 00H 00H 00H 00H 00H 00H 00H
SM0/FE
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 - - F7 E6 - - F6 E5 - - F5 E4 - - F4 E3 - - F3 E2 - - F2 E1 - - F1 E0 AO DPS F0
RESET VALUE 00H xxxxxxx0B xxxxxxx0B 00H 00H 00H
AE EC BE - B6 - 86 AD6 96 - A6 AD14 B6 WR SMOD0 D6 AC
AD ET2 BD PT2 B5 PT2H 85 AD5 95 - A5 AD13 B5 T1 - D5 F0
AC ES BC PS B4 PSH 84 AD4 94 - A4 AD12 B4 T0 POF2 D4 RS1
AB ET1 BB PT1 B3 PT1H 83 AD3 93 - A3 AD11 B3 INT1 GF1 D3 RS0
AA EX1 BA PX1 B2 PX1H 82 AD2 92 - A2 AD10 B2 INT0 GF0 D2 OV
A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 -
A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P 00H 00H 00H 00H 00H xxxxxxxxB FFH 00xx0000B FFH FFH FFH x0000000B x0000000B 00H
EA BF - B7 - 87 AD7 97 - A7 AD15 B7 RD SMOD1 D7 CY
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 07H
TMOD Timer Mode 89H GATE C/T * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2. Bit will not be affected by Reset. POF is not present in 80C52. 1996 Aug 16 5
M1
M0
GATE
C/T
M1
M0
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39
1
33
LCC
PQFP
17
29
11
23
18 Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
28 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE NC* EA P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6 P1.7 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1
12 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN ALE NC* EA P0.7/AD7
22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* P1.0/T2 P1.1/T2EX P1.2 P1.3 P1.4
* DO NOT CONNECT
SU00741A
* DO NOT CONNECT
SU00742A
PIN DESCRIPTIONS
PIN NUMBER MNEMONIC VSS VCC P0.0-0.7 DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O NAME AND FUNCTION Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
P1.0-P1.7
1-8
2-9
40-44, 1-3
I/O
1 2 3 4 5 6 7 8 P2.0-P2.7 21-28
2 3 4 5 6 7 8 9 24-31
40 41 42 43 44 1 2 3 18-25
I/O I I I/O I/O I/O I/O I/O I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register.
1996 Aug 16
6
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PIN DESCRIPTIONS (Continued)
PIN NUMBER MNEMONIC P3.0-P3.7 DIP 10-17 LCC 11, 13-19 QFP 5, 7-13 TYPE I/O NAME AND FUNCTION Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR auxiliary.0. With this bit set, ALE will be active only during a MOVX instruction. Program Store Enable: The read strobe to external program memory. When the 80C52/80C54/80C58 is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 7FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 7FFFH. If security bit 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier.
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE
30
33
27
O
PSEN
29
32
26
O
EA
31
35
29
I
XTAL1 XTAL2
19 18
21 20
15 14
I O
NOTE: To avoid "latch-up" effect at power-on, the voltage on any pin at any time must not be higher than VCC + 0.5V or VSS - 0.5V, respectively.
1996 Aug 16
7
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
TIMER 2 OPERATION Timer 2
Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes:Capture, Auto-reload (up or down counting) ,and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 2.
Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16-bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When a logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to the value stored in RCAP2L and RCAP2H. Timer 2 underflow sets the TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. The external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.
Capture Mode
In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register/SFR table). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set, and EXF2 like TF2 can generate an interrupt (which vectors to the same location as Timer 2 overflow interrupt. The Timer 2 interrupt service routine can interrogate TF2 and EXF2 to determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.).
Auto-Reload Mode (Up or Down Counter)
In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter (C/T2* in T2CON)) then programmed to count up or down. The counting direction is determined by bit DCEN(Down Counter Enable) which is located in the T2MOD register (see
(MSB) TF2 Symbol TF2 EXF2 Position T2CON.7 T2CON.6 EXF2 RCLK TCLK EXEN2 TR2 C/T2
(LSB) CP/RL2
Name and Significance Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK or TCLK = 1. Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1). Receive clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock. Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock. Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX. Start/stop control for Timer 2. A logic 1 starts the timer. Timer or counter select. (Timer 2) 0 = Internal timer (OSC/12) 1 = External event counter (falling edge triggered). Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if EXEN2 = 1. When cleared, auto-reloads will occur either with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
SU00728
RCLK TCLK EXEN2
T2CON.5 T2CON.4 T2CON.3
TR2 C/T2
T2CON.2 T2CON.1
CP/RL2
T2CON.0
Figure 1. Timer/Counter 2 (T2CON) Control Register 1996 Aug 16 8
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Table 2. Timer 2 Operating Modes
RCLK + TCLK 0 0 1 X CP/RL2 0 1 X X TR2 1 1 1 0 16-bit Auto-reload 16-bit Capture Baud rate generator (off) MODE
OSC
/ 12 C/T2 = 0 TL2 (8-bits) C/T2 = 1 TH2 (8-bits) TF2
T2 Pin
Control
TR2 Transition Detector
Capture Timer 2 Interrupt RCAP2L RCAP2H
T2EX Pin
EXF2
Control
EXEN2
SU00066
Figure 2. Timer 2 in Capture Mode
T2MOD
Address = 0C9H Not Bit Addressable -- Bit 7 -- 6 -- 5 -- 4 -- 3 -- 2 T2OE 1
Reset Value = XXXX XX00B
DCEN 0
Symbol -- T2OE DCEN *
Function Not implemented, reserved for future use.* Timer 2 Output Enable bit. See details in Programmable Clock-Out. Down Count Enable bit. When set, this allows Timer 2 to be configured as an up/down counter.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. Figure 3. Timer 2 Mode (T2MOD) Control Register
SU00746
1996 Aug 16
9
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
OSC
/ 12 C/T2 = 0 TL2 (8-BITS) C/T2 = 1 TH2 (8-BITS)
T2 PIN
CONTROL
TR2
RELOAD
TRANSITION DETECTOR
RCAP2L
RCAP2H TF2 TIMER 2 INTERRUPT
T2EX PIN
EXF2
CONTROL
EXEN2
SU00067
Figure 4. Timer 2 in Auto-Reload Mode (DCEN = 0)
(DOWN COUNTING RELOAD VALUE) FFH FFH
TOGGLE EXF2
OSC
/12
C/T2 = 0 OVERFLOW TL2 TH2 TF2 INTERRUPT
T2 PIN
C/T2 = 1 CONTROL TR2 COUNT DIRECTION 1 = UP 0 = DOWN RCAP2L RCAP2H T2EX PIN
(UP COUNTING RELOAD VALUE)
SU00730
Figure 5. Timer 2 Auto Reload Mode (DCEN = 1)
1996 Aug 16
10
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Timer 1 Overflow
NOTE: OSC. Freq. is divided by 2, not 12. /2 C/T2 = 0 TL2 (8-bits) C/T2 = 1 T2 Pin Control TH2 (8-bits) "1"
/2 "0" "1" SMOD "0" RCLK
OSC
/ 16 TR2 "1" Reload "0"
RX Clock
TCLK
Transition Detector
RCAP2L
RCAP2H
/ 16
TX Clock
T2EX Pin
EXF2
Timer 2 Interrupt
Control EXEN2 Note availability of additional external interrupt.
SU00068
Figure 6. Timer 2 in Baud Rate Generator Mode
Table 3.
Timer 2 Generated Commonly Used Baud Rates
Timer 2 Osc Freq 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H FF FF FF FF FE FB F2 FD F9 RCAP2L FF D9 B2 64 C8 1E AF 8F 57
The baud rates in modes 1 and 3 are determined by Timer 2's overflow rate given below: Modes 1 and 3 Baud Rates + Timer 2 Overflow Rate 16 The timer can be configured for either "timer" or "counter" operation. In many applications, it is configured for "timer" operation (C/T2*=0). Timer operation is different for Timer 2 when it is being used as a baud rate generator. Usually, as a timer it would increment every machine cycle (i.e., 1/12 the oscillator frequency). As a baud rate generator, it increments every state time (i.e., 1/2 the oscillator frequency). Thus the baud rate formula is as follows: Modes 1 and 3 Baud Rates = Oscillator Frequency [32 [65536 * (RCAP2H, RCAP2L)]] Where: (RCAP2H, RCAP2L)= The content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer. The Timer 2 as a baud rate generator mode shown in Figure 6, is valid only if RCLK and/or TCLK = 1 in T2CON register. Note that a rollover in TH2 does not set TF2, and will not generate an interrupt. Thus, the Timer 2 interrupt does not have to be disabled when Timer 2 is in the baud rate generator mode. Also if the EXEN2 (T2 external enable flag) is set, a 1-to-0 transition in T2EX (Timer/counter 2 trigger input) will set EXF2 (T2 external flag) but will not cause a reload from (RCAP2H, RCAP2L) to (TH2,TL2). Therefore when Timer 2 is in use as a baud rate generator, T2EX can be used as an additional external interrupt, if needed.
Baud Rate 375K 9.6K 2.8K 2.4K 1.2K 300 110 300 110
Baud Rate Generator Mode
Bits TCLK and/or RCLK in T2CON (Table 2) allow the serial port transmit and receive baud rates to be derived from either Timer 1 or Timer 2. When TCLK= 0, Timer 1 is used as the serial port transmit baud rate generator. When TCLK= 1, Timer 2 is used as the serial port transmit baud rate generator. RCLK has the same effect for the serial port receive baud rate. With these two bits, the serial port can have different receive and transmit baud rates - one generated by Timer 1, the other by Timer 2. Figure 6 shows the Timer 2 in baud rate generation mode. The baud rate generation mode is like the auto-reload mode,in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
1996 Aug 16
11
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
When Timer 2 is in the baud rate generator mode, one should not try to read or write TH2 and TL2. As a baud rate generator, Timer 2 is incremented every state time (osc/2) or asynchronously from pin T2; under these conditions, a read or write of TH2 or TL2 may not be accurate. The RCAP2 registers may be read, but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers. Table 3 shows commonly used baud rates and how they can be obtained from Timer 2.
To obtain the reload value for RCAP2H and RCAP2L, the above equation can be rewritten as: RCAP2H, RCAP2L + 65536 * f OSC Baud Rate
32
Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given for T2CON do not include the setting of the TR2 bit. Therefore, bit TR2 must be set, separately, to turn the timer on. see Table 4 for set-up of Timer 2 as a timer. Also see Table 5 for set-up of Timer 2 as a counter.
Summary Of Baud Rate Equations
Timer 2 is in baud rate generating mode. If Timer 2 is being clocked through pin T2(P1.0) the baud rate is: Baud Rate + Timer 2 Overflow Rate 16 If Timer 2 is being clocked internally, the baud rate is: Baud Rate + f OSC [65536 * (RCAP2H, RCAP2L)]]
POWER OFF FLAG3
The Power Off Flag (POF) is set by on-chip circuitry when the VCC level on the 80C54/80C58 rises from 0 to 5V. The POF bit can be set or cleared by software allowing a user to determine if the reset is the result of a power-on or a warm start after powerdown. The VCC level must remain above 3V for the POF to remain unaffected by the VCC level.
[32
Where fOSC= Oscillator Frequency
Table 4. Timer 2 as a Timer
T2CON MODE 16-bit Auto-Reload 16-bit Capture Baud rate generator receive and transmit same baud rate Receive only Transmit only INTERNAL CONTROL (Note 1) 00H 01H 34H 24H 14H EXTERNAL CONTROL (Note 2) 08H 09H 36H 26H 16H
Table 5. Timer 2 as a Counter
TMOD MODE 16-bit Auto-Reload INTERNAL CONTROL (Note 1) 02H 03H EXTERNAL CONTROL (Note 2) 0AH 0BH
NOTES: 1. Capture/reload occurs only on timer/counter overflow. 2. Capture/reload occurs on timer/counter overflow and a 1-to-0 transition on T2EX (P1.1) pin except when Timer 2 is used in the baud rate generator mode. 3. POF not present in 80C52.
1996 Aug 16
12
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put the device into Power Down.
Design Consideration
* When the idle mode is terminated by a hardware reset, the device
normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.
Reset
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on VCC and RST must come up at the same time for a proper start-up. Ports 1, 2, and 3 will asynchronously be driven to their reset condition when a voltage above VIH1 (min.) is applied to RESET.
ONCETM Mode
The ONCE ("On-Circuit Emulation") Mode facilitates testing and debugging of systems using the 80C52/54/58 without removing the device from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 80C52/54/58 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.
Idle Mode
In the idle mode (see Table 6), the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
Programmable Clock-Out
The 80C52/54/58 has a new feature. A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. to input the external clock for Timer/Counter 2, or 2. to output a 50% duty cycle clock ranging from 61Hz to 4MHz at a 16MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T2OE in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The Clock-Out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this equation: 4 Oscillator Frequency (65536 * RCAP2H, RCAP2L)
Power-Down Mode
To save even more power, a Power Down mode (see Table 6) can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 80C52/54/58 either a hardware reset or external interrupt can be used to exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INT0 and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the
In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.
Table 6. External Pin Status During Idle and Power-Down Mode
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
1996 Aug 16
13
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Enhanced UART
The UART operates in all of the usual modes that are described in the first section of Data Handbook IC20, 80C51-Based 8-Bit Microcontrollers. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 80C52/54/58 UART also fully supports multiprocessor communication as does the standard 80C51 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure 7). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 8. Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the "Given" address or the "Broadcast" address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 9. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave's address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are "don't care". The SADEN mask can be logically ANDed with the SADDR to create the "|Given" address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = SADEN = Given = 1100 0000 1111 1101 1100 00X0
Slave 1
SADDR = SADEN = Given =
1100 0000 1111 1110 1100 000X
In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = SADEN = Given = SADDR = SADEN = Given = SADDR = SADEN = Given = 1100 0000 1111 1001 1100 0XX0 1110 0000 1111 1010 1110 0X0X 1110 0000 1111 1100 1110 00XX
Slave 1
Slave 2
In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don't-cares. In most cases, interpreting the don't-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are leaded with 0s. This produces a given address of all "don't cares" as well as a Broadcast address of all "don't cares". this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.
1996 Aug 16
14
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
SCON Address = 98H Bit Addressable SM0/FE Bit: SM1 SM2 5 REN 4 TB8 3 RB8 2 Tl 1 Rl 0
Reset Value = 0000 0000B
7 6 (SMOD0 = 0/1)*
Symbol FE SM0 SM1
Function Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit. Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) Serial Port Mode Bit 1 SM0 SM1 Mode 0 0 1 1 0 1 0 1 0 1 2 3 Description shift register 8-bit UART 9-bit UART 9-bit UART Baud Rate** fOSC/12 variable fOSC/64 or fOSC/32 variable
SM2
Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. Enables serial reception. Set by software to enable reception. Clear by software to disable reception. The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received. In Mode 0, RB8 is not used. Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software.
REN TB8 RB8 Tl Rl
NOTE: *SMOD0 is located at PCON6. **fOSC = oscillator frequency
SU00043
Figure 7. SCON: Serial Port Control Register
D0
D1
D2
D3
D4
D5
D6
D7
D8
START BIT
DATA BYTE
ONLY IN MODE 2, 3
STOP BIT
SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) SM0 TO UART MODE CONTROL
SM0 / FE
SM1
SM2
REN
TB8
RB8
TI
RI
SCON (98H)
SMOD1
SMOD0
-
POF
GF1
GF0
PD
IDL
PCON (87H)
0 : SCON.7 = SM0 1 : SCON.7 = FE
SU00747
Figure 8. UART Framing Error Detection
1996 Aug 16
15
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
D0
D1
D2
D3
D4
D5
D6
D7
D8
SM0 1 1
SM1 1 0
SM2 1
REN 1
TB8 X
RB8
TI
RI
SCON (98H)
RECEIVED ADDRESS D0 TO D7 PROGRAMMED ADDRESS COMPARATOR
IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND "RECEIVED ADDRESS" = "PROGRAMMED ADDRESS" - WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES - WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.
SU00045
Figure 9. UART Multiprocessor Communication, Automatic Address Recognition
Interrupt Priority Structure
The 80C52/54/58 has a 6-source four-level interrupt structure. There are 3 SFRs associated with the interrupts on the 80C52/54/58. They are the IE and IP. (See Figures 10 and 11.) In addition, there is the IPH (Interrupt Priority High) register that makes the four-level interrupt structure possible. The IPH is located at SFR address B7H. The structure of the IPH register and a description of its bits is shown below: IPH (Interrupt Priority High) (B7H)
7 - 6 - 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H
PRIORITY BITS IPH.x 0 0 1 1 IP.x 0 1 0 1 INTERRUPT PRIORITY LEVEL Level 0 (lowest priority) Level 1 Level 2 Level 3 (highest priority)
IPH.0 IPH.1 IPH.2 IPH.3 IPH.4 IPH.5 IPH.6 IPH.7
PX0H PT0H PX1H PT1H PSH PT2H -- --
External interrupt 0 priority high Timer 0 interrupt priority high External interrupt 1 priority high Timer 1 interrupt priority high Serial Port interrupt high Timer 2 interrupt priority high Not implemented Not implemented
The priority scheme for servicing the interrupts is the same as that for the 80C51, except there are four interrupt levels on the 80C52/54/58 rather than two as on the 80C51. An interrupt will be serviced as long as an interrupt of equal or higher priority is not already being serviced. If an interrupt of equal or higher level priority is being serviced, the new interrupt will wait until it is finished before being serviced. If a lower priority level interrupt is being serviced, it will be stopped and the new interrupt serviced. When the new interrupt is finished, the lower priority level interrupt that was stopped will be completed.
The function of the IPH SFR is simple and when combined with the IP SFR determines the priority of each interrupt. The priority of each interrupt is determined as shown in the following table:
Table 7.
Interrupt Table
POLLING PRIORITY 1 2 3 4 5 6 7 REQUEST BITS IE0 TP0 IE1 TF1 R1, TI TF2, EXF2 CF, CCFn n = 0-4 HARDWARE CLEAR? N (L)1 Y N (L) Y (T) Y N N N Y (T)2 VECTOR ADDRESS 03H 0BH 13H 1BH 23H 2BH 33H X0 T0 X1 T1 SP T2 PCA
SOURCE
NOTES: 1. L = Level activated 2. T = Transition activated
1996 Aug 16
16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
7 IE0 (A8H) EA
6 --
5 ET2
4 ES
3 ET1
2 EX1
1 ET0
0 EX0
Enable Bit = 1 enables the interrupt. Enable Bit = 0 disables it. BIT IE.7 IE.6 IE.5 IE.4 IE.3 IE.2 IE.1 IE.0 SYMBOL EA -- ET2 ES ET1 EX1 ET0 EX0 FUNCTION Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually enabled or disabled by setting or clearing its enable bit. Timer 2 interrupt enable bit. Serial Port interrupt enable bit. Timer 1 interrupt enable bit. External interrupt 1 enable bit. Timer 0 interrupt enable bit. External interrupt 0 enable bit.
SU00743
Figure 10. IE Registers
7 IP0 (B8H) --
6 --
5 PT2
4 PS
3 PT1
2 PX1
1 PT0
0 PX0
Priority Bit = 1 assigns high priority Priority Bit = 0 assigns low priority BIT IP.7 IP.6 IP.5 IP.4 IP.3 IP.2 IP.1 IP.0 SYMBOL -- -- PT2 PS PT1 PX1 PT0 PX0 FUNCTION Not implemented, reserved for future use. Timer 2 interrupt priority bit. Serial Port interrupt priority bit. Timer 1 interrupt priority bit. External interrupt 1 priority bit. Timer 0 interrupt priority bit. External interrupt 0 priority bit.
SU00744
Figure 11. IP Registers
1996 Aug 16
17
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Reduced EMI Mode
The AO bit (AUXR.0) in the AUXR register when set disables the ALE output.
DPS BIT0 AUXR1
80C52/80C54/80C58 Reduced EMI Mode
AUXR (8EH)
7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 AO
DPTR1 DPTR0 DPH (83H) DPL (82H) EXTERNAL DATA MEMORY
AO:
Turns off ALE output. Figure 12. DPTR Structure
SU00745A
Dual Data Pointer Register (DPTR)
The dual DPTR structure (see Figure 12) is a way by which the 80C52/54/58 will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 that allows the program code to switch between them. DPTR Instructions The instructions that refer to DPTR refer to the data pointer that is currently selected using the AUXR1/bit 0 register. The six instructions that use the DPTR are as follows: INC DPTR MOV DPTR, #data16 MOV A, @ A+DPTR
4 - 3 - 2 - 1 - 0 DPS
* Register Name: AUXR1# * SFR Address: A2H * Reset Value: xxxxxxx0B
7 - 6 - 5 -
Increments the data pointer by 1 Loads the DPTR with a 16-bit constant Move code byte relative to DPTR to ACC Move external RAM (16-bit address) to ACC Move ACC to external RAM (16-bit address) Jump indirect relative to DPTR
MOVX A, @ DPTR MOVX @ DPTR , A JMP @ A + DPTR
Where: DPS = AUXR1/bit0 = Switches between DPTR0 and DPTR1. Select Reg DPTR0 DPTR1 DPS 0 1
The data pointer can be accessed on a byte-by-byte basis by specifying the Low or High byte in an instruction which accesses the SFRs. See application note AN458 for detailed operation
The DPS bit status whould be saved by software when switching between DPTR0 and DPTR1.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.5 15 1.5 UNIT C C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1996 Aug 16
18
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5.0V 10%; VSS = 0V SYMBOL VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC Input low voltage Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, RST Output low voltage, ports 1, 2, 38 Output low voltage, port 0, ALE, PSEN8, 7 Output high voltage, ports 1, 2, 3 3 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 36 Input leakage current, port 0 Power supply current (see Figure 20): Active mode @ 16MHz5 Idle mode @ 16MHz5 Power-down mode Internal reset pull-down resistor Pin capacitance10 (except EA) VCC = 4.5V IOL = 1.6mA2 VCC = 4.5V IOL = 3.2mA2 VCC = 4.5V IOH = -30A VCC = 4.5V IOH = -3.2mA VIN = 0.4V VIN = 2.0V See note 4 0.45 < VIN < VCC - 0.3 See note 5 Tamb = 0 to +70C Tamb = -40 to +85C 40 3 16 4 50 75 225 15 mA mA A A k pF VCC - 0.7 VCC - 0.7 -1 -50 -650 10 PARAMETER TEST CONDITIONS 4.5V < VCC < 5.5V LIMITS MIN -0.5 0.2VCC+0.9 0.7VCC TYP1 UNIT MAX 0.2VCC-0.1 VCC+0.5 VCC+0.5 0.4 0.4 V V V V V V V A A A
RRST CIO
NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the (VCC-0.7) specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 21 through 24 for ICC test conditions. Active Mode: ICC = 0.9 x FREQ + 1.1; Idle Mode: ICC = 0.18 x FREQ +1.0; See Figure 20. 6. This value applies to Tamb = 0C to +70C. For Tamb = -40C to +85C, ITL = -750A. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA (*NOTE: This is 85C specification.) Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF).
1996 Aug 16
19
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 16MHz CLOCK SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 16 16 16 16 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 750 492 8 0 12tCLCL 10tCLCL-133 2tCLCL-117 0 ns ns ns ns 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 15 14, 15 14, 15 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high 23 137 122 13 13 287 0 103 tCLCL-40 20 20 20 20 0 65 350 397 239 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 0 tCLCL+40 tCLCL-tCLCX tCLCL-tCHCX 20 20 275 275 147 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 13 13 13 13 13 13 13 13 13 13 13 13 PARAMETER Oscillator frequency Speed versions : E ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in4 0 37 207 10 32 142 82 0 tCLCL-25 5tCLCL-105 10 85 22 32 150 tCLCL-30 3tCLCL-45 3tCLCL-105 MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in4 PSEN low to address float
External Clock 17 17 17 17 High time Low time Rise time Fall time 20 20 ns ns ns ns
tXHDV 16 Clock rising edge to input data valid 492 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interfacing.
1996 Aug 16
20
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
AC ELECTRICAL CHARACTERISTICS
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 24MHz CLOCK SYMBOL 1/tCLCL FIGURE 13 PARAMETER Oscillator frequency Speed versions : I (24MHz) : N (33MHz) ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 505 283 3 0 17 17 17 5 5 12tCLCL 10tCLCL-133 2tCLCL-80 0 0 75 92 12 17 162 0 67 tCLCL-25 17 17 0 55 183 210 175 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 0 tCLCL+25 tCLCL-tCLCX tCLCL-tCHCX 5 5 360 167 5 150 150 118 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 40 45 0 5 80 0 55 0 17 128 10 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 32 90 105 140 17 80 65 0 tCLCL-25 5tCLCL-80 10 82 82 60 MIN 3.5 43 17 17 102 tCLCL-25 3tCLCL-45 3tCLCL-60 0 5 70 10 MAX 24 3.5 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 5 45 30 55 21 5 33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VARIABLE CLOCK4 MIN 3.5 MAX 33 MHz 33MHz CLOCK MIN MAX UNIT
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
13 13 13 13 13 13 13 13 13 13 13 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 14, 15 15 14, 15 14, 15 17 17 17 17 16 16 16 16
External Clock
tXHDV 16 Clock rising edge to input data valid 283 10tCLCL-133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C52/54/58 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz "AC Electrial Characteristics", page 20. 1996 Aug 16 21
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL =Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 13. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPF A0-A15 FROM PCH
SU00025
Figure 14. External Data Memory Read Cycle
1996 Aug 16
22
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX tQVWH
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0-P2.7 OR A8-A15 FROM DPF
A0-A15 FROM PCH
SU00026
Figure 15. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 16. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 17. External Clock Drive
1996 Aug 16
23
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
VCC-0.5
0.2VCC+0.9 VLOAD 0.2VCC-0.1
VLOAD+0.1V VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00717
SU00718
Figure 18. AC Testing Input/Output
Figure 19. Float Waveform
35
30 MAX ACTIVE MODE ICCMAX = 0.9 X FREQ. + 1.1 25
20 ICC mA 15 TYP ACTIVE MODE
10 MAX IDLE MODE 5 TYP IDLE MODE 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz 28MHz 32MHz 36MHz FREQ AT XTAL1
SU00768
Figure 20. ICC vs. FREQ Valid only within frequency specifications of the device under test
1996 Aug 16
24
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 21. ICC Test Condition, Active Mode All other pins are disconnected
Figure 22. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 23. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 24. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
1996 Aug 16
25
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
Security Bits
With none of the security bits programmed the code in the program memory can be verified. If the encryption table is programmed, the code will be encrypted when verified. When only security bit 1 (see Table 8) is programmed, MOVC instructions executed from external program memory are disabled from fetching code bytes from the
internal memory, EA is latched on Reset and all further programming of the EPROM is disabled. When security bits 1 and 2 are programmed, in addition to the above, verify mode is disabled.
Encryption Array
64 bytes of encryption array are initially unprogrammed (all 1s).
Table 8. Program Security Bits
PROGRAM LOCK BITS1, 2 SB1 1 2 U P SB2 U U PROTECTION DESCRIPTION No Program Security features enabled. (Code verify will still be encrypted by the Encryption Array if programmed.) MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on Reset, and further programming of the EPROM is disabled.
NOTES: 1. P - programmed. U - unprogrammed. 2. Any other combination of the security bits is not defined.
80C52 ROM CODE SUBMISSION
When submitting ROM code for the 80C52, the following must be specified: 1. 8k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS 0000H to 1FFFH 2000H to 201FH 2020H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
2020H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send key file.
1996 Aug 16
26
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
80C54 ROM CODE SUBMISSION
When submitting ROM code for the 80C54, the following must be specified: 1. 16k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. ADDRESS 0000H to 3FFFH 4000H to 401FH 4020H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
4020H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM.
If the ROM Code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box, and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send key file.
1996 Aug 16
27
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
80C58 ROM CODE SUBMISSION
When submitting ROM code for the 80C58, the following must be specified: 1. 32k byte user ROM data 2. 64 byte ROM encryption key 3. ROM security bits. If submitting a file, the format is as follows: ADDRESS 0000H to 7FFFH 8000H to 801FH 8020H CONTENT DATA KEY SEC BIT(S) 7:0 7:0 0 COMMENT User ROM Data ROM Encryption Key FFH = no encryption ROM Security Bit 1 0 = enable security 1 = disable security ROM Security Bit 2 0 = enable security 1 = disable security
8020H
SEC
1
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM. If the ROM code file does not include the options, the following information must be included with the ROM code. For each of the following check the appropriate box and send to Philips along with the code: Security Bit #1: Security Bit #2: Encryption:
V V V
Enabled Enabled No
V V V
Disabled Disabled Yes If Yes, must send key file.
1996 Aug 16
28
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1996 Aug 16
29
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1996 Aug 16
30
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
1996 Aug 16
31
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C52/80C54/80C58
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.

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